Joachim Strömbergson ec77b15eb8

FPGA: Increase SPI speed ...

- Change SPI clock from 16 CPU cyles/flank to one cycle/flank
- Remove separate flank length wait states in the FSM

Signed-off-by: Joachim Strömbergson <joachim@assured.se>

2024-06-19 15:48:07 +02:00

..

core

FPGA: Increase SPI speed

2024-06-19 15:48:07 +02:00

data

A construction of a minimal SPI master.

2024-06-11 15:28:29 +02:00

fw

Remove redundant RAM address and data scrambling

2024-06-13 12:54:47 +02:00

rtl

A construction of a minimal SPI master.

2024-06-11 15:28:29 +02:00

tb

Rename to TK1

2022-10-26 09:20:02 +02:00

tools

hw/tool: UDI/UDS storage

2024-04-03 11:27:00 +02:00

application_fpga.bin.sha256

Remove redundant RAM address and data scrambling

2024-06-13 12:54:47 +02:00

config.vlt

Config verilator lint to ignore known 3rd-party warnings; let warnings be fatal

2023-03-01 13:37:31 +01:00

firmware.bin.sha512

Remove redundant RAM address and data scrambling

2024-06-13 12:54:47 +02:00

Makefile

CI: Enable linting in CI again. See #182.

2024-06-17 15:37:13 +02:00