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tillitis-key/hw
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Joachim Strömbergson ec77b15eb8
FPGA: Increase SPI speed 
- Change SPI clock from 16 CPU cyles/flank to one cycle/flank
- Remove separate flank length wait states in the FSM

Signed-off-by: Joachim Strömbergson <joachim@assured.se>
2024-06-19 15:48:07 +02:00
..
application_fpga FPGA: Increase SPI speed 2024-06-19 15:48:07 +02:00
boards Add injection molded plastic case 2023-12-11 13:48:39 +01:00
production_test Print warning if the programmer device permissions are incorrect 2023-03-21 14:38:29 +01:00