Daniel Jobson bf1ac5c237

Remove YosysHQ copyright and fix name typo ...

The removal is coordinated and approved by YosysHQ, and are removed
to keep our headers uniform. These files were written on behalf of
Tillitis.
Two typos was corrected as well.

2024-09-30 15:01:31 +02:00

..

clk_reset_gen

Doc: Add README for the clock and reset core.

2024-08-29 16:06:59 +02:00

fw_ram

Doc: Add README for the fw_ram.

2024-08-29 16:06:59 +02:00

picorv32

FPGA: Ignore warnings about blocking assignment in clocked processes

2024-06-17 15:37:13 +02:00

ram

FPGA: Move RAM address and data scrambling into the RAM module.

2024-08-30 10:53:13 +02:00

rom

Doc: Add README for the ROM core.

2024-08-29 16:06:59 +02:00

timer

Update Verilog version to 2005 for linting

2024-04-24 08:44:08 +02:00

tk1

Remove YosysHQ copyright and fix name typo

2024-09-30 15:01:31 +02:00

touch_sense

Update Verilog version to 2005 for linting

2024-04-24 08:44:08 +02:00

trng

Update Verilog version to 2005 for linting

2024-04-24 08:44:08 +02:00

uart

FPGA: Increase clock frequency to 21 MHz

2024-08-20 13:45:00 +02:00

uds

Remove YosysHQ copyright and fix name typo

2024-09-30 15:01:31 +02:00