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tillitis-key/hw/application_fpga/core
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Joachim Strömbergson a2ecaffa75
(fpga) Debug build and sim target. 
1. Debug tk1 core with initial changes to fw-app-mode.

       2. Debug testbench with fixes related to name changes for
       address and data RAM randomization.

       3. Debug test6 that checks SPI access.

Signed-off-by: Joachim Strömbergson <joachim@assured.se>
2024-08-28 13:54:10 +02:00
..
picorv32 FPGA: Ignore warnings about blocking assignment in clocked processes 2024-06-17 15:37:13 +02:00
timer Update Verilog version to 2005 for linting 2024-04-24 08:44:08 +02:00
tk1 (fpga) Debug build and sim target. 2024-08-28 13:54:10 +02:00
touch_sense Update Verilog version to 2005 for linting 2024-04-24 08:44:08 +02:00
trng Update Verilog version to 2005 for linting 2024-04-24 08:44:08 +02:00
uart FPGA: Increase clock frequency to 21 MHz 2024-08-20 13:45:00 +02:00
uds Update Verilog version to 2005 for linting 2024-04-24 08:44:08 +02:00