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tillitis-key/hw/application_fpga
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Joachim Strömbergson a2ecaffa75
(fpga) Debug build and sim target. 
1. Debug tk1 core with initial changes to fw-app-mode.

       2. Debug testbench with fixes related to name changes for
       address and data RAM randomization.

       3. Debug test6 that checks SPI access.

Signed-off-by: Joachim Strömbergson <joachim@assured.se>
2024-08-28 13:54:10 +02:00
..
core (fpga) Debug build and sim target. 2024-08-28 13:54:10 +02:00
data A construction of a minimal SPI master. 2024-06-11 15:28:29 +02:00
fw FPGA: Add SPI access control logic 2024-08-26 14:09:19 +02:00
rtl FPGA: Increase clock frequency to 21 MHz 2024-08-20 13:45:00 +02:00
tb Rename to TK1 2022-10-26 09:20:02 +02:00
tools hw/tool: UDI/UDS storage 2024-04-03 11:27:00 +02:00
application_fpga.bin.sha256 FPGA: Increase clock frequency to 21 MHz 2024-08-20 13:45:00 +02:00
config.vlt Config verilator lint to ignore known 3rd-party warnings; let warnings be fatal 2023-03-01 13:37:31 +01:00
firmware.bin.sha512 FPGA: Update names for RAM randomization API 2024-07-10 13:45:26 +02:00
Makefile fpga: Include SPI master during linting 2024-08-26 14:09:19 +02:00