tillitis-key/hw/application_fpga
2024-03-20 16:39:53 +01:00
..
core Clean up code and silence warnings after linting 2024-03-20 16:39:53 +01:00
data Change name of pin constraint file to match tk1 pcb 2023-07-04 09:04:29 +02:00
fw fw: Change ASLR name in MMIO 2024-03-19 14:36:31 +01:00
rtl Clean up code and silence warnings after linting 2024-03-20 16:39:53 +01:00
tb Rename to TK1 2022-10-26 09:20:02 +02:00
tools Support incremental builds for the bitstream. 2024-03-20 16:39:45 +01:00
application_fpga.bin.sha256 Update the bitstream hash 2024-03-20 14:36:56 +01:00
config.vlt Config verilator lint to ignore known 3rd-party warnings; let warnings be fatal 2023-03-01 13:37:31 +01:00
firmware.bin.sha512 FW: Force the CPU to hang on errors 2024-03-14 15:48:10 +01:00
Makefile Disable non-zero exit for verilog linter in CI, see issue 182. 2024-03-20 16:39:53 +01:00