tillitis-key/hw/application_fpga
2022-10-17 11:15:26 +02:00
..
core Change ADDR_CTRL to be a pulsed start_stop signal 2022-10-14 08:50:30 +02:00
data Make initial public release 2022-09-19 08:51:11 +02:00
fw testfw: tidy, clean-up, fmt 2022-10-17 11:15:26 +02:00
rtl Merge branch 'fw_ram' 2022-10-13 13:16:53 +02:00
tb Update verilator top level module to match rom module changes 2022-10-06 13:59:01 +02:00
tools Add default values to tpt.py 2022-09-21 09:49:07 +02:00
Makefile Merge branch 'fw_ram' 2022-10-13 13:16:53 +02:00