Jonas Thörnblad 48cbb55d6e Add incoming and outgoing CTS (Clear To Send) signals for the FPGA ... to let the CH552 and FPGA signal each other that it is OK to send UART data. The CTS signals indicate "OK to send" if high. If an incoming CTS signal goes low, the receiver of that signal should immediatly stop sending UART data.		2024-12-17 17:18:45 +01:00
..
clk_reset_gen	FPGA: Format verilog code	2024-10-22 12:04:19 +02:00
fw_ram	Doc: fix typo of system mode in readme	2024-11-13 14:13:02 +01:00
picorv32	FPGA: Ignore warnings about blocking assignment in clocked processes	2024-06-17 15:37:13 +02:00
ram	Doc: move implementation details of RAM scrambling to RAM core	2024-11-20 15:48:49 +01:00
rom	Fix typo	2024-11-14 16:35:50 +01:00
timer	tb: make timer core testbench selftesting	2024-11-27 08:10:15 +01:00
tk1	tb: Make tb_tk1_spi_master.v selftesting	2024-12-09 13:55:42 +01:00
touch_sense	tb: Make touch_sense selftesting	2024-12-09 13:55:42 +01:00
trng	tb: Make trng selftesting	2024-12-09 13:55:43 +01:00
uart	Add incoming and outgoing CTS (Clear To Send) signals for the FPGA	2024-12-17 17:18:45 +01:00
uds	Harmonize the naming of firmware and app mode.	2024-11-12 15:13:59 +01:00