Daniel Jobson 395d241ed3 uart: add framing error handling ... - Checks the stop bit, if it is not valid the data is discarded and enters a error state. Only checks first stop bit. - Adds an error state to the RX FSM. The core starts in this state to not assume a valid idle rx line on start up. Prevents accepting frames on a constant low rx line and filling the fifo. - bugfix: always reset bitrate_ctr when leaving state ERX_BITS and remove unused bitrate_ctr counter in ERX_STOP		2025-10-27 08:54:31 +01:00
..
clk_reset_gen	fpga/testfw: Update clock frequency to 24 MHz	2025-02-11 13:50:04 +01:00
fw_ram	fpga/fw: Rename system_mode to app_mode	2025-02-27 14:20:37 +01:00
picorv32	FPGA: Ignore warnings about blocking assignment in clocked processes	2024-06-17 15:37:13 +02:00
ram	Doc: move implementation details of RAM scrambling to RAM core	2024-11-20 15:48:49 +01:00
rom	Fix typo	2024-11-14 16:35:50 +01:00
timer	tb: make timer core testbench selftesting	2024-11-27 08:10:15 +01:00
tk1	fpga: Bump tk1 core version to 6	2025-05-20 11:27:07 +02:00
touch_sense	tb: Make touch_sense selftesting	2024-12-09 13:55:42 +01:00
trng	tb: Make trng selftesting	2024-12-09 13:55:43 +01:00
uart	uart: add framing error handling	2025-10-27 08:54:31 +01:00
uds	doc: Update documentation about syscalls	2025-02-27 14:35:22 +01:00