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tillitis-key/hw/application_fpga/tb
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Michael Cardell Widerkrantz 050e0f2673
fpga: Format Verilog
2025-02-11 14:37:29 +01:00
..
application_fpga_sim.v fpga: Format Verilog 2025-02-11 14:37:29 +01:00
application_fpga_verilator.cc fpga: Introduce CTS signals for UART 2025-02-11 13:50:04 +01:00
reset_gen_sim.v Align module name with its file name. 2024-11-28 16:09:59 +01:00
tb_application_fpga_sim.v fpga: Introduce CTS signals for UART 2025-02-11 13:50:04 +01:00
trng_sim.v Add verilog file for TRNG simulation 2024-11-28 16:10:00 +01:00