Daniel Lublin 2bb62af183 Update bit divisor calc in verilator's uart to our current 18 MHz		2022-10-03 13:11:53 +02:00
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core	Update bit counter to match 18 MHz clock frequency	2022-09-30 10:04:37 +02:00
data	Make initial public release	2022-09-19 08:51:11 +02:00
fw	Adjust flashing after frequency bump	2022-10-03 08:06:29 +02:00
rtl	Merge branch 'pll'	2022-09-30 10:06:48 +02:00
tb	Update bit divisor calc in verilator's uart to our current 18 MHz	2022-10-03 13:11:53 +02:00
tools	Add default values to tpt.py	2022-09-21 09:49:07 +02:00
Makefile	Fix Verilator sim by adding separate reset generator	2022-10-03 12:55:24 +02:00