mirror of
https://github.com/tillitis/tillitis-key1.git
synced 2024-07-11 13:52:16 +00:00
326 lines
9.3 KiB
Verilog
326 lines
9.3 KiB
Verilog
//======================================================================
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//
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// tb_uds.v
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// -----------
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// Testbench for the UDS core.
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//
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//
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// Author: Joachim Strombergson
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// Copyright (C) 2022 - Tillitis AB
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// SPDX-License-Identifier: GPL-2.0-only
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//
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//======================================================================
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`default_nettype none
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module tb_uds();
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//----------------------------------------------------------------
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// Internal constant and parameter definitions.
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//----------------------------------------------------------------
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parameter DEBUG = 1;
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parameter CLK_HALF_PERIOD = 1;
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parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD;
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localparam ADDR_UDS_FIRST = 8'h10;
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localparam ADDR_UDS_LAST = 8'h17;
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//----------------------------------------------------------------
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// Register and Wire declarations.
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//----------------------------------------------------------------
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reg [31 : 0] cycle_ctr;
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reg [31 : 0] error_ctr;
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reg [31 : 0] tc_ctr;
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reg tb_monitor;
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reg tb_clk;
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reg tb_reset_n;
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reg tb_fw_app_mode;
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reg tb_cs;
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reg [7 : 0] tb_address;
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wire [31 : 0] tb_read_data;
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//----------------------------------------------------------------
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// Device Under Test.
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//----------------------------------------------------------------
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uds dut(
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.clk(tb_clk),
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.reset_n(tb_reset_n),
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.fw_app_mode(tb_fw_app_mode),
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.cs(tb_cs),
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.address(tb_address),
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.read_data(tb_read_data)
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);
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//----------------------------------------------------------------
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// clk_gen
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//
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// Always running clock generator process.
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//----------------------------------------------------------------
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always
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begin : clk_gen
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#CLK_HALF_PERIOD;
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tb_clk = !tb_clk;
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end // clk_gen
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//----------------------------------------------------------------
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// sys_monitor()
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//
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// An always running process that creates a cycle counter and
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// conditionally displays information about the DUT.
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//----------------------------------------------------------------
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always
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begin : sys_monitor
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cycle_ctr = cycle_ctr + 1;
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#(CLK_PERIOD);
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if (tb_monitor)
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begin
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dump_dut_state();
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end
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end
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//----------------------------------------------------------------
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// dump_dut_state()
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//
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// Dump the state of the dump when needed.
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//----------------------------------------------------------------
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task dump_dut_state;
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begin : dump_dut_state
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integer i;
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$display("State of DUT at cycle: %08d", cycle_ctr);
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$display("------------");
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$display("Inputs and outputs:");
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$display("fw_app_mode: 0x%1x", tb_fw_app_mode);
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$display("cs: 0x%1x, address: 0x%02x, read_data: 0x%08x", tb_cs, tb_address, tb_read_data);
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$display("");
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$display("Internal state:");
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$display("tmp_read_ready: 0x%1x, tmp_read_data: 0x%08x", dut.tmp_ready, dut.tmp_read_data);
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for (i = 0 ; i < 8 ; i = i + 1) begin
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$display("uds_reg[%1d]: 0x%08x, uds_rd_reg[%1d]: 0x%1x", i, dut.uds_reg[i], i, dut.uds_rd_reg[i]);
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end
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$display("");
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$display("");
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end
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endtask // dump_dut_state
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//----------------------------------------------------------------
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// reset_dut()
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//
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// Toggle reset to put the DUT into a well known state.
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//----------------------------------------------------------------
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task reset_dut;
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begin
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$display("--- Toggle reset.");
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tb_reset_n = 0;
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#(2 * CLK_PERIOD);
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tb_reset_n = 1;
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end
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endtask // reset_dut
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//----------------------------------------------------------------
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// display_test_result()
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//
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// Display the accumulated test results.
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//----------------------------------------------------------------
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task display_test_result;
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begin
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if (error_ctr == 0)
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begin
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$display("--- All %02d test cases completed successfully", tc_ctr);
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end
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else
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begin
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$display("--- %02d tests completed - %02d test cases did not complete successfully.",
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tc_ctr, error_ctr);
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end
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end
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endtask // display_test_result
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//----------------------------------------------------------------
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// init_sim()
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//
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// Initialize all counters and testbed functionality as well
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// as setting the DUT inputs to defined values.
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//----------------------------------------------------------------
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task init_sim;
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begin
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cycle_ctr = 0;
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error_ctr = 0;
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tc_ctr = 0;
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tb_monitor = 0;
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tb_clk = 1'h0;
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tb_reset_n = 1'h1;
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tb_fw_app_mode = 1'h0;
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tb_cs = 1'h0;
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tb_address = 8'h0;
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end
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endtask // init_sim
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//----------------------------------------------------------------
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// read_word()
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//
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// Read a data word from the given address in the DUT.
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// the word read will be available in the global variable
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// read_data.
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//----------------------------------------------------------------
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task read_word(input [11 : 0] address);
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begin : read_word
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reg [31 : 0] read_data;
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tb_address = address;
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tb_cs = 1'h1;
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#(CLK_HALF_PERIOD);
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read_data = tb_read_data;
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#(CLK_HALF_PERIOD);
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tb_cs = 1'h0;
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if (DEBUG)
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begin
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$display("--- Reading 0x%08x from 0x%02x.", read_data, address);
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$display("");
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end
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end
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endtask // read_word
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//----------------------------------------------------------------
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// test1()
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//----------------------------------------------------------------
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task test1;
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begin
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tc_ctr = tc_ctr + 1;
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$display("");
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$display("--- test1: started.");
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$display("--- test1: Filling uds with known values.");
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dut.uds_reg[0] = 32'hf0f0f0f0;
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dut.uds_reg[1] = 32'he1e1e1e1;
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dut.uds_reg[2] = 32'hd2d2d2d2;
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dut.uds_reg[3] = 32'hc3c3c3c3;
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dut.uds_reg[4] = 32'hb4b4b4b4;
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dut.uds_reg[5] = 32'ha5a5a5a5;
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dut.uds_reg[6] = 32'h96969696;
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dut.uds_reg[7] = 32'h87878787;
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$display("--- test1: Dumping DUT state to show UDS contents");
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dump_dut_state();
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$display("--- test1: Reading UDS words.");
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read_word(ADDR_UDS_FIRST + 0);
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read_word(ADDR_UDS_FIRST + 1);
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read_word(ADDR_UDS_FIRST + 2);
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$display("--- test1: Dumping state again to see read bits.");
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dump_dut_state();
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$display("--- test1: Reading rest of the words.");
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read_word(ADDR_UDS_FIRST + 3);
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read_word(ADDR_UDS_FIRST + 4);
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read_word(ADDR_UDS_FIRST + 5);
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read_word(ADDR_UDS_FIRST + 6);
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read_word(ADDR_UDS_FIRST + 7);
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$display("--- test1: Dumping state again to see read bits.");
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dump_dut_state();
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$display("--- test1: Reading UDS words again.");
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$display("--- test1: This should return all zeros.");
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read_word(ADDR_UDS_FIRST + 0);
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read_word(ADDR_UDS_FIRST + 1);
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read_word(ADDR_UDS_FIRST + 2);
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read_word(ADDR_UDS_FIRST + 3);
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read_word(ADDR_UDS_FIRST + 4);
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read_word(ADDR_UDS_FIRST + 5);
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read_word(ADDR_UDS_FIRST + 6);
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read_word(ADDR_UDS_FIRST + 7);
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$display("--- test1: Resetting DUT.");
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$display("--- test1: This should allow access again.");
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reset_dut();
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$display("--- test1: Filling uds with new known values.");
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dut.uds_reg[0] = 32'h0f0f0f0f;
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dut.uds_reg[1] = 32'h1e1e1e1e;
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dut.uds_reg[2] = 32'h2d2d2d2d;
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dut.uds_reg[3] = 32'h3c3c3c3c;
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dut.uds_reg[4] = 32'h4b4b4b4b;
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dut.uds_reg[5] = 32'h5a5a5a5a;
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dut.uds_reg[6] = 32'h69696969;
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dut.uds_reg[7] = 32'h78787878;
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$display("--- test1: Dumping state again to see read bits.");
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dump_dut_state();
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$display("--- test1: Reading UDS words in changed order.");
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read_word(ADDR_UDS_FIRST + 7);
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read_word(ADDR_UDS_FIRST + 6);
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read_word(ADDR_UDS_FIRST + 4);
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read_word(ADDR_UDS_FIRST + 3);
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read_word(ADDR_UDS_FIRST + 1);
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read_word(ADDR_UDS_FIRST + 0);
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read_word(ADDR_UDS_FIRST + 5);
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read_word(ADDR_UDS_FIRST + 2);
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$display("--- test1: Reading UDS words again.");
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$display("--- test1: This should return all zeros.");
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read_word(ADDR_UDS_FIRST + 0);
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read_word(ADDR_UDS_FIRST + 1);
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read_word(ADDR_UDS_FIRST + 2);
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read_word(ADDR_UDS_FIRST + 3);
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read_word(ADDR_UDS_FIRST + 4);
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read_word(ADDR_UDS_FIRST + 5);
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read_word(ADDR_UDS_FIRST + 6);
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read_word(ADDR_UDS_FIRST + 7);
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$display("--- test1: completed.");
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$display("");
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end
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endtask // test1
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//----------------------------------------------------------------
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// uds_test
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//----------------------------------------------------------------
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initial
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begin : uds_test
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$display("");
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$display(" -= Testbench for uds started =-");
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$display(" ===========================");
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$display("");
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init_sim();
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reset_dut();
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test1();
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display_test_result();
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$display("");
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$display(" -= Testbench for uds completed =-");
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$display(" =============================");
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$display("");
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$finish;
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end // uds_test
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endmodule // tb_uds
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//======================================================================
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// EOF tb_uds.v
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//======================================================================
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