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https://github.com/tillitis/tillitis-key1.git
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Updated README, completed testcase and cleaned up the testbench
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
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Joachim Strömbergson
dehanj
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de7f273f71
commit
1e97e27e66
@ -3,5 +3,19 @@
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Unique Device Secret core
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## Introduction
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This core store and protect the Unique Device Secret. The
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storage is implemented in discrete registers. The contents can be read once between chip reset, and only if the system is in not in application access mode.
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This core store and protect the Unique Device Secret (UDS) asset. The
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UDS can be accessed as eight separate 32-bit words. The words can be
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accessed in any order, but a given word can only be accessed once
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between reset cycles. The words can only be accessed as long as the
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fw_app_mode input is low, implying that the CPU is executing the FW.
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Each UDS words has a companion read bit that is set when the word is
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accessed. This means that the even if the chip select (cs) control
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input is forced high, the content will become all zero when the read
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bit has been set after one cycle.
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## Implementation
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The UDS words are implemented in discrete registers.
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@ -19,26 +19,21 @@ module tb_uds();
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// Internal constant and parameter definitions.
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//----------------------------------------------------------------
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parameter DEBUG = 1;
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parameter DUMP_WAIT = 0;
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parameter CLK_HALF_PERIOD = 1;
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parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD;
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localparam ADDR_NAME0 = 8'h00;
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localparam ADDR_NAME1 = 8'h01;
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localparam ADDR_VERSION = 8'h02;
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localparam ADDR_UDS_FIRST = 8'h10;
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localparam ADDR_UDS_LAST = 8'h17;
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localparam ADDR_UDS_FIRST = 8'h10;
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localparam ADDR_UDS_LAST = 8'h17;
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//----------------------------------------------------------------
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// Register and Wire declarations.
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//----------------------------------------------------------------
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reg [31 : 0] cycle_ctr;
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reg [31 : 0] error_ctr;
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reg [31 : 0] tc_ctr;
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reg tb_monitor;
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reg [31 : 0] cycle_ctr;
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reg [31 : 0] error_ctr;
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reg [31 : 0] tc_ctr;
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reg tb_monitor;
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reg tb_clk;
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reg tb_reset_n;
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@ -47,8 +42,6 @@ module tb_uds();
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reg [7 : 0] tb_address;
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wire [31 : 0] tb_read_data;
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reg [31 : 0] read_data;
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//----------------------------------------------------------------
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// Device Under Test.
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@ -102,13 +95,19 @@ module tb_uds();
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task dump_dut_state;
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begin : dump_dut_state
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integer i;
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$display("State of DUT");
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$display("State of DUT at cycle: %08d", cycle_ctr);
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$display("------------");
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$display("Cycle: %08d", cycle_ctr);
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$display("Inputs and outputs:");
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$display("fw_app_mode: 0x%1x", tb_fw_app_mode);
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$display("cs: 0x%1x, address: 0x%02x, read_data: 0x%08x", tb_cs, tb_address, tb_read_data);
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$display("");
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$display("Internal state:");
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$display("tmp_read_ready: 0x%1x, tmp_read_data: 0x%08x", dut.tmp_ready, dut.tmp_read_data);
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for (i = 0 ; i < 8 ; i = i + 1) begin
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$display("uds_reg[%1d]: 0x%08x, uds_rd_reg[%1d]: 0x%1x",
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i, dut.uds_reg[i], i, dut.uds_rd_reg[i]);
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$display("uds_reg[%1d]: 0x%08x, uds_rd_reg[%1d]: 0x%1x", i, dut.uds_reg[i], i, dut.uds_rd_reg[i]);
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end
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$display("");
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$display("");
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end
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@ -180,12 +179,17 @@ module tb_uds();
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// read_data.
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//----------------------------------------------------------------
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task read_word(input [11 : 0] address);
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begin
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tb_address = address;
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tb_cs = 1;
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#(CLK_PERIOD);
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begin : read_word
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reg [31 : 0] read_data;
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tb_address = address;
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tb_cs = 1'h1;
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#(CLK_HALF_PERIOD);
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read_data = tb_read_data;
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tb_cs = 0;
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#(CLK_HALF_PERIOD);
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tb_cs = 1'h0;
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if (DEBUG)
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begin
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@ -202,11 +206,20 @@ module tb_uds();
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task test1;
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begin
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tc_ctr = tc_ctr + 1;
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tb_monitor = 1'h0;
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$display("");
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$display("--- test1: started.");
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$display("--- test1: Filling uds with known values.");
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dut.uds_reg[0] = 32'hf0f0f0f0;
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dut.uds_reg[1] = 32'he1e1e1e1;
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dut.uds_reg[2] = 32'hd2d2d2d2;
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dut.uds_reg[3] = 32'hc3c3c3c3;
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dut.uds_reg[4] = 32'hb4b4b4b4;
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dut.uds_reg[5] = 32'ha5a5a5a5;
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dut.uds_reg[6] = 32'h96969696;
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dut.uds_reg[7] = 32'h87878787;
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$display("--- test1: Dumping DUT state to show UDS contents");
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dump_dut_state();
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@ -229,6 +242,7 @@ module tb_uds();
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dump_dut_state();
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$display("--- test1: Reading UDS words again.");
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$display("--- test1: This should return all zeros.");
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read_word(ADDR_UDS_FIRST + 0);
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read_word(ADDR_UDS_FIRST + 1);
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read_word(ADDR_UDS_FIRST + 2);
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@ -239,22 +253,35 @@ module tb_uds();
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read_word(ADDR_UDS_FIRST + 7);
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$display("--- test1: Resetting DUT.");
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$display("--- test1: This should allow access again.");
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reset_dut();
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$display("--- test1: Filling uds with new known values.");
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dut.uds_reg[0] = 32'h0f0f0f0f;
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dut.uds_reg[1] = 32'h1e1e1e1e;
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dut.uds_reg[2] = 32'h2d2d2d2d;
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dut.uds_reg[3] = 32'h3c3c3c3c;
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dut.uds_reg[4] = 32'h4b4b4b4b;
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dut.uds_reg[5] = 32'h5a5a5a5a;
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dut.uds_reg[6] = 32'h69696969;
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dut.uds_reg[7] = 32'h78787878;
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$display("--- test1: Dumping state again to see read bits.");
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dump_dut_state();
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$display("--- test1: Reading UDS words.");
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read_word(ADDR_UDS_FIRST + 0);
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read_word(ADDR_UDS_FIRST + 1);
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read_word(ADDR_UDS_FIRST + 2);
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read_word(ADDR_UDS_FIRST + 3);
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read_word(ADDR_UDS_FIRST + 4);
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read_word(ADDR_UDS_FIRST + 5);
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read_word(ADDR_UDS_FIRST + 6);
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$display("--- test1: Reading UDS words in changed order.");
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read_word(ADDR_UDS_FIRST + 7);
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read_word(ADDR_UDS_FIRST + 6);
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read_word(ADDR_UDS_FIRST + 4);
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read_word(ADDR_UDS_FIRST + 3);
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read_word(ADDR_UDS_FIRST + 1);
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read_word(ADDR_UDS_FIRST + 0);
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read_word(ADDR_UDS_FIRST + 5);
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read_word(ADDR_UDS_FIRST + 2);
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$display("--- test1: Reading UDS words again.");
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$display("--- test1: This should return all zeros.");
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read_word(ADDR_UDS_FIRST + 0);
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read_word(ADDR_UDS_FIRST + 1);
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read_word(ADDR_UDS_FIRST + 2);
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@ -267,7 +294,7 @@ module tb_uds();
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$display("--- test1: completed.");
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$display("");
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end
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endtask // tes1
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endtask // test1
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//----------------------------------------------------------------
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@ -286,8 +313,8 @@ module tb_uds();
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display_test_result();
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$display("");
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$display(" -= Testbench for uds started =-");
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$display(" ===========================");
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$display(" -= Testbench for uds completed =-");
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$display(" =============================");
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$display("");
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$finish;
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end // uds_test
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