dehanj 1e34ddcfa6 Update linter to Verilog-2005		2024-03-19 10:45:37 +01:00
..
core	Explicity make uart_core.rx_data a wire (#140)	2023-08-16 10:43:04 +02:00
data	Change name of pin constraint file to match tk1 pcb	2023-07-04 09:04:29 +02:00
fw	Add void to function signatures meant to be used without args	2024-03-19 08:41:39 +01:00
rtl	Verilog 2001 rule; use wires for assignments, not registers. (#139)	2023-08-16 10:44:18 +02:00
tb	Rename to TK1	2022-10-26 09:20:02 +02:00
tools	Correct to new path	2023-01-13 15:42:46 +01:00
application_fpga.bin.sha256	FW: Force the CPU to hang on errors	2024-03-14 15:48:10 +01:00
config.vlt	Config verilator lint to ignore known 3rd-party warnings; let warnings be fatal	2023-03-01 13:37:31 +01:00
firmware.bin.sha512	FW: Force the CPU to hang on errors	2024-03-14 15:48:10 +01:00
Makefile	Update linter to Verilog-2005	2024-03-19 10:45:37 +01:00