Joachim Strömbergson 09df7ae97f FPGA: Fix linting of tk1 core ... Add simultion models of udi_rom and sb_rbga_drv to lint-top target. Add ignore statements in tb_sb_rgba_drv to silence Verilator on parameters and signals not used in the sim model. Use RGBLEDEN in simulation model Signed-off-by: Joachim Strömbergson <joachim@assured.se>		2024-06-10 14:22:59 +02:00
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core	FPGA: Fix linting of tk1 core	2024-06-10 14:22:59 +02:00
data	Change name of pin constraint file to match tk1 pcb	2023-07-04 09:04:29 +02:00
fw	fw: Remove unused header includes	2024-03-26 13:09:06 +01:00
rtl	Clean up code and silence warnings after linting	2024-03-20 16:39:53 +01:00
tb	Rename to TK1	2022-10-26 09:20:02 +02:00
tools	hw/tool: UDI/UDS storage	2024-04-03 11:27:00 +02:00
application_fpga.bin.sha256	Update hash of bitstream and firmware	2024-03-26 13:09:06 +01:00
config.vlt	Config verilator lint to ignore known 3rd-party warnings; let warnings be fatal	2023-03-01 13:37:31 +01:00
firmware.bin.sha512	Update hash of bitstream and firmware	2024-03-26 13:09:06 +01:00
Makefile	Change filename personalize.py to patch_uds_udi.py	2024-03-26 13:07:11 +01:00