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tillitis-key/hw
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Joachim Strömbergson 09df7ae97f
FPGA: Fix linting of tk1 core 
Add simultion models of udi_rom and sb_rbga_drv
      to lint-top target.

      Add ignore statements in tb_sb_rgba_drv to silence
      Verilator on parameters and signals not used in
      the sim model.

      Use RGBLEDEN in simulation model

Signed-off-by: Joachim Strömbergson <joachim@assured.se>
2024-06-10 14:22:59 +02:00
..
application_fpga
FPGA: Fix linting of tk1 core
2024-06-10 14:22:59 +02:00
boards
Add injection molded plastic case
2023-12-11 13:48:39 +01:00
production_test
Print warning if the programmer device permissions are incorrect
2023-03-21 14:38:29 +01:00