Joachim Strömbergson 00599549e3 FPGA: Add system reset API ... Add API address to trigger system reset. When written to will send system_reset signal to the reset generator, which then perform a complete reset cycle of the FPGA system. Signed-off-by: Joachim Strömbergson <joachim@assured.se>		2024-08-20 13:25:22 +02:00
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application_fpga.v	FPGA: Add system reset API	2024-08-20 13:25:22 +02:00
clk_reset_gen.v	FPGA: Add system reset API	2024-08-20 13:25:22 +02:00
fw_ram.v	Verilog 2001 rule; use wires for assignments, not registers. (#139)	2023-08-16 10:44:18 +02:00
ram.v	Implement cs0 and cs1 as logic equations, not muxes	2024-03-20 14:36:55 +01:00
rom.v	Clean up code and silence warnings after linting	2024-03-20 16:39:53 +01:00