5 commits

Author	SHA1	Message	Date
Daniel Jobson	1941a22007	Doc: move implementation details of RAM scrambling to RAM core	2024-11-20 15:48:49 +01:00
Jonas Thörnblad	3514d7ef3c	FPGA: Format verilog code	2024-10-22 12:04:19 +02:00
Joachim Strömbergson	35052e50cb	FPGA: Move RAM address and data scrambling into the RAM module. ... Move the logic implementing the RAM address and data scrambling, descrambling into the RAM module. This cleans up the top level, and makes it easier to change the scrambling without chaning the top. In order to do correct scrambling the address to the RAM core must be 16 bits, not 15. Clean up some minor details at the top level, fixing text aligment and grouping of ports in instances. Signed-off-by: Joachim Strömbergson <joachim@assured.se>	2024-08-30 10:53:13 +02:00
Joachim Strömbergson	2d769c5751	Doc: add README for the RAM. ... Signed-off-by: Joachim Strömbergson <joachim@assured.se>	2024-08-29 16:06:59 +02:00
Joachim Strömbergson	d1cff273d7	FPGA: Move all sub modules into separate cores ... Signed-off-by: Joachim Strömbergson <joachim@assured.se>	2024-08-29 16:06:58 +02:00