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3514d7ef3c
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2 Commits

Author SHA1 Message Date
Jonas Thörnblad
3514d7ef3c
FPGA: Format verilog code 2024-10-22 12:04:19 +02:00
Joachim Strömbergson
b2ca3f2ea0
Fix Verilator sim by adding separate reset generator 2022-10-03 12:55:24 +02:00