Git-Mirrors/tillitis-key
1
0
Fork 0
mirror of https://github.com/tillitis/tillitis-key1.git synced 2025-05-02 06:06:24 -04:00
Code Issues Projects Releases Packages Wiki Activity
527 commits 34 branches 17 tags 31 MiB
Commit graph

3 commits

Author SHA1 Message Date
Jonas Thörnblad
330146ba3a
Rename top level simulation files 
* Rename application_fpga_vsim.v and reset_gen_vsim.v to
  application_fpga_sim.v and reset_gen_sim.v
* Update Makefile
* Fix a typo
 2024-11-12 15:33:33 +01:00
Jonas Thörnblad
3514d7ef3c
FPGA: Format verilog code 2024-10-22 12:04:19 +02:00
Joachim Strömbergson
b2ca3f2ea0
Fix Verilator sim by adding separate reset generator 2022-10-03 12:55:24 +02:00