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Change UDS address to three bits to match input port connection 'addr'

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Signed-off-by: Joachim Strömbergson <joachim@assured.se>
This commit is contained in:
Joachim Strömbergson 2024-03-19 13:57:17 +01:00 • committed by Michael Cardell Widerkrantz
parent bbde62d3f5
commit f364b523cf
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GPG key ID: D3DB3DDF57E704E5
2 changed files with 8 additions and 17 deletions
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11
hw/application_fpga/core/uds/rtl/uds.v
View file

@ -20,19 +20,12 @@ module uds(
input wire fw_app_mode, input wire fw_app_mode,
input wire cs, input wire cs,
input wire [7 : 0] address, input wire [2 : 0] address,
output wire [31 : 0] read_data, output wire [31 : 0] read_data,
output wire ready output wire ready
); );
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
localparam ADDR_UDS_FIRST = 8'h10;
localparam ADDR_UDS_LAST = 8'h17;
//---------------------------------------------------------------- //----------------------------------------------------------------
// Registers including update variables and write enable. // Registers including update variables and write enable.
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -98,7 +91,6 @@ module uds(
if (cs) begin if (cs) begin
tmp_ready = 1'h1; tmp_ready = 1'h1;
if ((address >= ADDR_UDS_FIRST) && (address <= ADDR_UDS_LAST)) begin
if (!fw_app_mode) begin if (!fw_app_mode) begin
if (uds_rd_reg[address[2 : 0]] == 1'h0) begin if (uds_rd_reg[address[2 : 0]] == 1'h0) begin
uds_rd_we = 1'h1; uds_rd_we = 1'h1;
@ -106,7 +98,6 @@ module uds(
end end
end end
end end
end
endmodule // uds endmodule // uds
//====================================================================== //======================================================================

4
hw/application_fpga/rtl/application_fpga.v
View file

@ -115,7 +115,7 @@ module application_fpga(
/* verilator lint_off UNOPTFLAT */ /* verilator lint_off UNOPTFLAT */
reg uds_cs; reg uds_cs;
/* verilator lint_on UNOPTFLAT */ /* verilator lint_on UNOPTFLAT */
reg [7 : 0] uds_address; reg [2 : 0] uds_address;
wire [31 : 0] uds_read_data; wire [31 : 0] uds_read_data;
wire uds_ready; wire uds_ready;
@ -404,7 +404,7 @@ module application_fpga(
timer_write_data = cpu_wdata; timer_write_data = cpu_wdata;
uds_cs = 1'h0; uds_cs = 1'h0;
uds_address = cpu_addr[9 : 2]; uds_address = cpu_addr[4 : 2];
uart_cs = 1'h0; uart_cs = 1'h0;
uart_we = |cpu_wstrb; uart_we = |cpu_wstrb;