diff --git a/hw/application_fpga/core/uds/rtl/uds.v b/hw/application_fpga/core/uds/rtl/uds.v
index cc3bf45..d214c05 100644
--- a/hw/application_fpga/core/uds/rtl/uds.v
+++ b/hw/application_fpga/core/uds/rtl/uds.v
@@ -20,19 +20,12 @@ module uds(
 	   input wire           fw_app_mode,
 
            input wire           cs,
-           input wire  [7 : 0]  address,
+           input wire  [2 : 0]  address,
            output wire [31 : 0] read_data,
            output wire          ready
           );
 
 
-  //----------------------------------------------------------------
-  // Internal constant and parameter definitions.
-  //----------------------------------------------------------------
-  localparam ADDR_UDS_FIRST    = 8'h10;
-  localparam ADDR_UDS_LAST     = 8'h17;
-
-
   //----------------------------------------------------------------
   // Registers including update variables and write enable.
   //----------------------------------------------------------------
@@ -98,13 +91,11 @@ module uds(
       if (cs) begin
 	tmp_ready = 1'h1;
 
-	if ((address >= ADDR_UDS_FIRST) && (address <= ADDR_UDS_LAST)) begin
-	  if (!fw_app_mode) begin
-            if (uds_rd_reg[address[2 : 0]] == 1'h0) begin
-              uds_rd_we     = 1'h1;
-            end
-	  end
-        end
+	if (!fw_app_mode) begin
+          if (uds_rd_reg[address[2 : 0]] == 1'h0) begin
+            uds_rd_we     = 1'h1;
+          end
+	end
       end
     end
 endmodule // uds
diff --git a/hw/application_fpga/rtl/application_fpga.v b/hw/application_fpga/rtl/application_fpga.v
index 00a229c..91a6efb 100644
--- a/hw/application_fpga/rtl/application_fpga.v
+++ b/hw/application_fpga/rtl/application_fpga.v
@@ -115,7 +115,7 @@ module application_fpga(
   /* verilator lint_off UNOPTFLAT */
   reg           uds_cs;
   /* verilator lint_on UNOPTFLAT */
-  reg  [7 : 0]  uds_address;
+  reg  [2 : 0]  uds_address;
   wire [31 : 0] uds_read_data;
   wire          uds_ready;
 
@@ -404,7 +404,7 @@ module application_fpga(
       timer_write_data    = cpu_wdata;
 
       uds_cs              = 1'h0;
-      uds_address         = cpu_addr[9 : 2];
+      uds_address         = cpu_addr[4 : 2];
 
       uart_cs             = 1'h0;
       uart_we             = |cpu_wstrb;