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(fpga) Add note about allowed values and fixed default values.

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Added note that prescaler and timer shoild be set to nonzero
       values. Added note that prescaler and timer can't be changed
       when the timer is running.

       Changed reset values for timer and prescalet to one.

Signed-off-by: Joachim Strömbergson <joachim@assured.se>
This commit is contained in:
Joachim Strömbergson 2024-08-15 14:08:27 +02:00
parent 6d8c0aff64
commit dc72d9907d
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GPG Key ID: 5DDC7C542422EC8D
2 changed files with 5 additions and 2 deletions
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3
hw/application_fpga/core/timer/README.md
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@ -37,3 +37,6 @@ The following addresses define the API for the timer:
FREE_RUNNING_BIT 0
```
ADDR_PRESCALER and ADDR_TIMER should be set to a non-negative value (default are one.)
Note that these values can't be changed when the timer is running.

4
hw/application_fpga/core/timer/rtl/timer.v
View File

@ -106,8 +106,8 @@ module timer(
start_reg <= 1'h0;
stop_reg <= 1'h0;
free_running_reg <= 1'h0;
prescaler_reg <= 32'h0;
timer_reg <= 32'h0;
prescaler_reg <= 32'h1;
timer_reg <= 32'h1;
end
else begin
start_reg <= start_new;