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(fpga) Update README with info on the free running mode.
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
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# timer
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A simple timer with prescaler.
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Timer with prescaler and support for free running mode.
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## Introduction
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This core implements a simple timer with a prescaler. The prescaler
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allows measurement of time durations rather than cycles. If for
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example setting the prescaler to the clock frequency in Hertz, the
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timer will count seconds.
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This core implements a simple timer with a prescaler and support for a
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free running mode.
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The prescaler allows measurement of time durations rather than
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cycles. If for example setting the prescaler to the clock frequency in
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Hertz, the timer will count seconds. After (prescaler * timer) number
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of cycles the timer will stop. Checking status of the timer can be
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done by reading the STATUS_RUNNING_BIT. If set to zero, the timer has
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completed.
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If the free running mode is set (default off), the counter will not
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stup when the number of cycles defined by (prescaler * timer) has been
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reached. Instead the timer continues until the CTRL_STOP_BIT is
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asserted. Note that in free running mode, the ADDR_PRESCALER shall be
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set to one (1).
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## API
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The following addresses define the API for the timer:
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```
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ADDR_CTRL: 0x08
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CTRL_START_BIT: 0
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CTRL_STOP_BIT: 1
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ADDR_CTRL: 0x08
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CTRL_START_BIT: 0
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CTRL_STOP_BIT: 1
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ADDR_STATUS: 0x09
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ADDR_STATUS: 0x09
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STATUS_RUNNING_BIT: 0
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ADDR_PRESCALER: 0x0a
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ADDR_TIMER: 0x0b
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ADDR_PRESCALER: 0x0a
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ADDR_TIMER: 0x0b
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ADDR_FREE_RUNNING: 0x0c
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FREE_RUNNING_BIT 0
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```
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## Details
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The core consists of the timer_core module (in timer_core.v) and a top
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level wrapper, timer (in timer.v). The top level wrapper implements
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the API, while the timer_core implements the actual timer
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functionality.
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The timer counter and the prescaler counter are both 32 bits.
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When enabled the counter counts down one integer value per cycle.
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The timer will stop when reaching final zero (given by prescaler times the initial value of the timer)
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and the running flag will be lowered.
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