diff --git a/hw/application_fpga/core/timer/README.md b/hw/application_fpga/core/timer/README.md
index 902dc9d..e7b465c 100644
--- a/hw/application_fpga/core/timer/README.md
+++ b/hw/application_fpga/core/timer/README.md
@@ -37,3 +37,6 @@ The following addresses define the API for the timer:
 	FREE_RUNNING_BIT    0
 
 ```
+
+ADDR_PRESCALER and ADDR_TIMER should be set to a non-negative value (default are one.)
+Note that these values can't be changed when the timer is running.
diff --git a/hw/application_fpga/core/timer/rtl/timer.v b/hw/application_fpga/core/timer/rtl/timer.v
index 1ddbeb4..a62d02d 100644
--- a/hw/application_fpga/core/timer/rtl/timer.v
+++ b/hw/application_fpga/core/timer/rtl/timer.v
@@ -106,8 +106,8 @@ module timer(
 	start_reg        <= 1'h0;
 	stop_reg         <= 1'h0;
 	free_running_reg <= 1'h0;
-	prescaler_reg    <= 32'h0;
-	timer_reg        <= 32'h0;
+	prescaler_reg    <= 32'h1;
+	timer_reg        <= 32'h1;
       end
       else begin
 	start_reg <= start_new;