Squashed commit of the following:

Silence lint on intentional combinatinal loops
    Use better instance names, and a single lint pragma for all macros
    Remove unused pointer update signals
    Silence lint on wires where not all bits are used
    Change fw_app_mode to be an input port to allow access control
    Remove redundant, unused wire mem_busy
    Add lint pragma to ignore debug register only enabled by a define
    Remove clk and reset_n ports from the ROM
    Adding note and lint pragma for rom address width
    Fix incorrect register widths in uart_core
    Assign all 16 bits in LUT config
    Silence lint warnings on macro instances
    Correct bit extraction for core addresses to be eight bits wide
    Correct the bit width of cdi_mem_we wire
    Add specific output file for logging lint issues
    Correct bit width of tmp_ready to match one bit ready port

hw/application_fpga/rtl/application_fpga.v

@@ -69,7 +69,9 @@ module application_fpga(
 
   wire          cpu_valid;
   wire [03 : 0] cpu_wstrb;
+  /* verilator lint_off UNUSED */
   wire [31 : 0] cpu_addr;
+  /* verilator lint_on UNUSED */
   wire [31 : 0] cpu_wdata;
 
   /* verilator lint_off UNOPTFLAT */
@@ -195,9 +197,6 @@ module application_fpga(
 
 
   rom rom_inst(
-               .clk(clk),
-               .reset_n(reset_n),
-
                .cs(rom_cs),
                .address(rom_address),
                .read_data(rom_read_data),
@@ -353,29 +352,29 @@ module application_fpga(
 
       trng_cs             = 1'h0;
       trng_we             = |cpu_wstrb;
-      trng_address        = cpu_addr[10 : 2];
+      trng_address        = cpu_addr[9 : 2];
       trng_write_data     = cpu_wdata;
 
       timer_cs            = 1'h0;
       timer_we            = |cpu_wstrb;
-      timer_address       = cpu_addr[10 : 2];
+      timer_address       = cpu_addr[9 : 2];
       timer_write_data    = cpu_wdata;
 
       uds_cs              = 1'h0;
-      uds_address         = cpu_addr[10 : 2];
+      uds_address         = cpu_addr[9 : 2];
 
       uart_cs             = 1'h0;
       uart_we             = |cpu_wstrb;
-      uart_address        = cpu_addr[10 : 2];
+      uart_address        = cpu_addr[9 : 2];
       uart_write_data     = cpu_wdata;
 
       touch_sense_cs      = 1'h0;
       touch_sense_we      = |cpu_wstrb;
-      touch_sense_address = cpu_addr[10 : 2];
+      touch_sense_address = cpu_addr[9 : 2];
 
       mta1_cs             = 1'h0;
       mta1_we             = |cpu_wstrb;
-      mta1_address        = cpu_addr[10 : 2];
+      mta1_address        = cpu_addr[9 : 2];
       mta1_write_data     = cpu_wdata;
 
       if (cpu_valid && !muxed_ready_reg) begin

hw/application_fpga/rtl/clk_reset_gen.v

@@ -46,36 +46,38 @@ module clk_reset_gen #(parameter RESET_CYCLES = 200)
   //----------------------------------------------------------------
   // Core instantiations.
   //----------------------------------------------------------------
+  /* verilator lint_off PINMISSING */
+
   // Use the FPGA internal High Frequency OSCillator as clock source.
   // 00: 48MHz, 01: 24MHz, 10: 12MHz, 11: 6MHz
-  /* verilator lint_off PINMISSING */
   SB_HFOSC #(.CLKHF_DIV("0b10")
-	     ) u_hfosc (.CLKHFPU(1'b1),.CLKHFEN(1'b1),.CLKHF(hfosc_clk));
-  /* verilator lint_on PINMISSING */
+	     ) hfosc_inst (.CLKHFPU(1'b1),.CLKHFEN(1'b1),.CLKHF(hfosc_clk));
 
 
-  // PLL to generate a new clock frequency based on the HFOSC clock.
-  /* verilator lint_off PINMISSING */
+  // Use a PLL to generate a new clock frequency based on the HFOSC clock.
   SB_PLL40_CORE #(
 		  .FEEDBACK_PATH("SIMPLE"),
 		  .DIVR(4'b0000),	// DIVR =  0
 		  .DIVF(7'b0101111),	// DIVF = 47
 		  .DIVQ(3'b101),	// DIVQ =  5
 		  .FILTER_RANGE(3'b001)	// FILTER_RANGE = 1
-		  ) uut (
+		  ) pll_inst (
 			 .RESETB(1'b1),
 			 .BYPASS(1'b0),
 			 .REFERENCECLK(hfosc_clk),
 			 .PLLOUTCORE(pll_clk)
 			 );
-  /* verilator lint_on PINMISSING */
 
-  // Use a global buffer to distribute the clock.
-  SB_GB SB_GB_i (
+
+  // Use a Global Buffer to distribute the clock.
+  SB_GB gb_inst (
 		 .USER_SIGNAL_TO_GLOBAL_BUFFER (pll_clk),
 		 .GLOBAL_BUFFER_OUTPUT (clk)
 		 );
 
+  /* verilator lint_on PINMISSING */
+
+
   //----------------------------------------------------------------
   // reg_update.
   //----------------------------------------------------------------

hw/application_fpga/rtl/rom.v

@@ -15,11 +15,10 @@
 `default_nettype none
 
 module rom(
-	   input wire           clk,
-	   input wire           reset_n,
-
 	   input wire           cs,
+  /* verilator lint_off UNUSED */
 	   input wire  [11 : 0] address,
+  /* verilator lint_on UNUSED */
 	   output wire [31 : 0] read_data,
 	   output wire          ready
            );
@@ -35,6 +34,9 @@ module rom(
   // each pair store 256 32bit words.
   // The size of the EBR allocated to memory must match the
   // size of the firmware file generated by the Makefile.
+  //
+  // Max size for the ROM is 3072 words, and the address is
+  // 12 bits to support ROM with this number of words.
   localparam EBR_MEM_SIZE = `BRAM_FW_SIZE;
   reg [31 : 0] memory [0 : (EBR_MEM_SIZE - 1)];
   initial $readmemh(`FIRMWARE_HEX, memory);
@@ -56,7 +58,10 @@ module rom(
   //----------------------------------------------------------------
   always @*
     begin : rom_logic
+
+      /* verilator lint_off WIDTH */
       rom_rdata = memory[address];
+      /* verilator lint_on WIDTH */
       rom_ready = cs;
     end