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Squashed commit of the following:

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Silence lint on intentional combinatinal loops
    Use better instance names, and a single lint pragma for all macros
    Remove unused pointer update signals
    Silence lint on wires where not all bits are used
    Change fw_app_mode to be an input port to allow access control
    Remove redundant, unused wire mem_busy
    Add lint pragma to ignore debug register only enabled by a define
    Remove clk and reset_n ports from the ROM
    Adding note and lint pragma for rom address width
    Fix incorrect register widths in uart_core
    Assign all 16 bits in LUT config
    Silence lint warnings on macro instances
    Correct bit extraction for core addresses to be eight bits wide
    Correct the bit width of cdi_mem_we wire
    Add specific output file for logging lint issues
    Correct bit width of tmp_ready to match one bit ready port
This commit is contained in:
Joachim Strömbergson 2022-10-06 13:23:30 +02:00
parent 2bb62af183
commit c35e7680ea
No known key found for this signature in database
GPG key ID: 865B8A548EA61679
15 changed files with 102 additions and 72 deletions
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2
hw/application_fpga/core/uart/rtl/uart.v
View file

@ -58,7 +58,9 @@ module uart(
input wire cs,
input wire we,
input wire [7 : 0] address,
/* verilator lint_off UNUSED */
input wire [31 : 0] write_data,
/* verilator lint_on UNUSED */
output wire [31 : 0] read_data,
output wire ready
);

26
hw/application_fpga/core/uart/rtl/uart_core.v
View file

@ -17,7 +17,7 @@
//
// Author: Joachim Strombergson
// Copyright (c) 2014, Secworks Sweden AB
//
//
// SPDX-License-Identifier: BSD-2-Clause
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
@ -96,8 +96,8 @@ module uart_core(
reg [7 : 0] rxd_byte_reg;
reg rxd_byte_we;
reg [4 : 0] rxd_bit_ctr_reg;
reg [4 : 0] rxd_bit_ctr_new;
reg [3 : 0] rxd_bit_ctr_reg;
reg [3 : 0] rxd_bit_ctr_new;
reg rxd_bit_ctr_we;
reg rxd_bit_ctr_rst;
reg rxd_bit_ctr_inc;
@ -124,8 +124,8 @@ module uart_core(
reg [7 : 0] txd_byte_new;
reg txd_byte_we;
reg [4 : 0] txd_bit_ctr_reg;
reg [4 : 0] txd_bit_ctr_new;
reg [3 : 0] txd_bit_ctr_reg;
reg [3 : 0] txd_bit_ctr_new;
reg txd_bit_ctr_we;
reg txd_bit_ctr_rst;
reg txd_bit_ctr_inc;
@ -175,14 +175,14 @@ module uart_core(
rxd0_reg <= 1'b0;
rxd_reg <= 1'b0;
rxd_byte_reg <= 8'h0;
rxd_bit_ctr_reg <= 5'h0;
rxd_bit_ctr_reg <= 4'h0;
rxd_bitrate_ctr_reg <= 16'h0;
rxd_syn_reg <= 0;
erx_ctrl_reg <= ERX_IDLE;
txd_reg <= 1'b1;
txd_byte_reg <= 8'h0;
txd_bit_ctr_reg <= 5'h0;
txd_bit_ctr_reg <= 4'h0;
txd_bitrate_ctr_reg <= 16'h0;
txd_ready_reg <= 1'b1;
etx_ctrl_reg <= ETX_IDLE;
@ -247,11 +247,11 @@ module uart_core(
//----------------------------------------------------------------
always @*
begin: rxd_bit_ctr
rxd_bit_ctr_new = 5'h0;
rxd_bit_ctr_new = 4'h0;
rxd_bit_ctr_we = 1'b0;
if (rxd_bit_ctr_rst) begin
rxd_bit_ctr_new = 5'h0;
rxd_bit_ctr_new = 4'h0;
rxd_bit_ctr_we = 1'b1;
end
@ -294,11 +294,11 @@ module uart_core(
//----------------------------------------------------------------
always @*
begin: txd_bit_ctr
txd_bit_ctr_new = 5'h0;
txd_bit_ctr_new = 4'h0;
txd_bit_ctr_we = 1'h0;
if (txd_bit_ctr_rst) begin
txd_bit_ctr_new = 5'h0;
txd_bit_ctr_new = 4'h0;
txd_bit_ctr_we = 1'h1;
end
@ -391,7 +391,7 @@ module uart_core(
rxd_byte_we = 1;
rxd_bit_ctr_inc = 1;
rxd_bitrate_ctr_rst = 1;
if (rxd_bit_ctr_reg == data_bits - 1) begin
if (rxd_bit_ctr_reg == (data_bits - 1)) begin
erx_ctrl_new = ERX_STOP;
erx_ctrl_we = 1;
end
@ -501,7 +501,7 @@ module uart_core(
end
else begin
txd_new = txd_byte_reg[txd_bit_ctr_reg];
txd_new = txd_byte_reg[txd_bit_ctr_reg[2 : 0]];
txd_we = 1;
txd_bit_ctr_inc = 1;
end

2
hw/application_fpga/core/uart/rtl/uart_fifo.v
View file

@ -57,12 +57,10 @@ module uart_fifo(
reg [7: 0] in_ptr_reg;
reg [7: 0] in_ptr_new;
reg in_ptr_inc;
reg in_ptr_we;
reg [7: 0] out_ptr_reg;
reg [7: 0] out_ptr_new;
reg out_ptr_inc;
reg out_ptr_we;
reg [7: 0] byte_ctr_reg;