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Add yosys flags to optimize synthesis

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* -abc2, run two passes of 'abc' for slightly improved logic density
  * -device u, optimize timing for up5k device
  * -dff, run 'abc'/'abc9' with -dff (D flip flop) option

  Update digest of application_fpga.bin
This commit is contained in:
Jonas Thörnblad 2024-10-17 13:07:05 +02:00 committed by Daniel Jobson
parent 3514d7ef3c
commit 8af048fb9a
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GPG Key ID: 3707A9DBF4BB8F1A
2 changed files with 3 additions and 2 deletions
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3
hw/application_fpga/Makefile
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@ -335,7 +335,8 @@ synth.json: $(FPGA_SRC) $(VERILOG_SRCS) $(PICORV32_SRCS) bram_fw.hex \
$(YOSYS_FLAG) \
-DBRAM_FW_SIZE=$(BRAM_FW_SIZE) \
-DFIRMWARE_HEX=\"$(P)/bram_fw.hex\" \
-p 'synth_ice40 -dsp -top application_fpga -json $@; write_verilog -attr2comment synth.v' \
-p 'synth_ice40 -abc2 -device u -dff -dsp -top application_fpga -json $@' \
-p 'write_verilog -attr2comment synth.v' \
$(filter %.v, $^)
application_fpga_par.json: synth.json $(P)/data/$(PIN_FILE)

2
hw/application_fpga/application_fpga.bin.sha256
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@ -1 +1 @@
8dcd61bda632cee5a11c2eb1fc2b36f4948a9ef872e5826b23cc147c8bd2c975 application_fpga.bin
6585aafa13727dc5bf560f34c457048ca3d13ee6ab502c2afc737b1e70fa5a00 application_fpga.bin