From 8af048fb9a96ce95f6ecc065bcecf9d60b883f5f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jonas=20Th=C3=B6rnblad?= Date: Thu, 17 Oct 2024 13:07:05 +0200 Subject: [PATCH] Add yosys flags to optimize synthesis * -abc2, run two passes of 'abc' for slightly improved logic density * -device u, optimize timing for up5k device * -dff, run 'abc'/'abc9' with -dff (D flip flop) option Update digest of application_fpga.bin --- hw/application_fpga/Makefile | 3 ++- hw/application_fpga/application_fpga.bin.sha256 | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/hw/application_fpga/Makefile b/hw/application_fpga/Makefile index 43acfba..784d410 100644 --- a/hw/application_fpga/Makefile +++ b/hw/application_fpga/Makefile @@ -335,7 +335,8 @@ synth.json: $(FPGA_SRC) $(VERILOG_SRCS) $(PICORV32_SRCS) bram_fw.hex \ $(YOSYS_FLAG) \ -DBRAM_FW_SIZE=$(BRAM_FW_SIZE) \ -DFIRMWARE_HEX=\"$(P)/bram_fw.hex\" \ - -p 'synth_ice40 -dsp -top application_fpga -json $@; write_verilog -attr2comment synth.v' \ + -p 'synth_ice40 -abc2 -device u -dff -dsp -top application_fpga -json $@' \ + -p 'write_verilog -attr2comment synth.v' \ $(filter %.v, $^) application_fpga_par.json: synth.json $(P)/data/$(PIN_FILE) diff --git a/hw/application_fpga/application_fpga.bin.sha256 b/hw/application_fpga/application_fpga.bin.sha256 index 8c9dff9..ab43462 100644 --- a/hw/application_fpga/application_fpga.bin.sha256 +++ b/hw/application_fpga/application_fpga.bin.sha256 @@ -1 +1 @@ -8dcd61bda632cee5a11c2eb1fc2b36f4948a9ef872e5826b23cc147c8bd2c975 application_fpga.bin +6585aafa13727dc5bf560f34c457048ca3d13ee6ab502c2afc737b1e70fa5a00 application_fpga.bin