diff --git a/hw/application_fpga/Makefile b/hw/application_fpga/Makefile
index 43acfba..784d410 100644
--- a/hw/application_fpga/Makefile
+++ b/hw/application_fpga/Makefile
@@ -335,7 +335,8 @@ synth.json: $(FPGA_SRC) $(VERILOG_SRCS) $(PICORV32_SRCS) bram_fw.hex \
 		$(YOSYS_FLAG) \
 		-DBRAM_FW_SIZE=$(BRAM_FW_SIZE) \
 		-DFIRMWARE_HEX=\"$(P)/bram_fw.hex\" \
-		-p 'synth_ice40 -dsp -top application_fpga -json $@; write_verilog -attr2comment synth.v' \
+		-p 'synth_ice40 -abc2 -device u -dff -dsp -top application_fpga -json $@' \
+		-p 'write_verilog -attr2comment synth.v' \
 		$(filter %.v, $^)
 
 application_fpga_par.json: synth.json $(P)/data/$(PIN_FILE)
diff --git a/hw/application_fpga/application_fpga.bin.sha256 b/hw/application_fpga/application_fpga.bin.sha256
index 8c9dff9..ab43462 100644
--- a/hw/application_fpga/application_fpga.bin.sha256
+++ b/hw/application_fpga/application_fpga.bin.sha256
@@ -1 +1 @@
-8dcd61bda632cee5a11c2eb1fc2b36f4948a9ef872e5826b23cc147c8bd2c975  application_fpga.bin
+6585aafa13727dc5bf560f34c457048ca3d13ee6ab502c2afc737b1e70fa5a00  application_fpga.bin