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Add yosys flags to optimize synthesis
* -abc2, run two passes of 'abc' for slightly improved logic density * -device u, optimize timing for up5k device * -dff, run 'abc'/'abc9' with -dff (D flip flop) option Update digest of application_fpga.bin
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8dcd61bda632cee5a11c2eb1fc2b36f4948a9ef872e5826b23cc147c8bd2c975 application_fpga.bin
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6585aafa13727dc5bf560f34c457048ca3d13ee6ab502c2afc737b1e70fa5a00 application_fpga.bin
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