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Increase clock frequency to 21 MHz
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
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@ -68,7 +68,7 @@ module clk_reset_gen #(parameter RESET_CYCLES = 200)
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SB_PLL40_CORE #(
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SB_PLL40_CORE #(
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.FEEDBACK_PATH("SIMPLE"),
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.FEEDBACK_PATH("SIMPLE"),
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.DIVR(4'b0000), // DIVR = 0
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.DIVR(4'b0000), // DIVR = 0
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.DIVF(7'b0101111), // DIVF = 47
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.DIVF(7'b0110111), // DIVF = 55
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.DIVQ(3'b101), // DIVQ = 5
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.DIVQ(3'b101), // DIVQ = 5
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.FILTER_RANGE(3'b001) // FILTER_RANGE = 1
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.FILTER_RANGE(3'b001) // FILTER_RANGE = 1
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) pll_inst (
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) pll_inst (
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