diff --git a/hw/application_fpga/rtl/clk_reset_gen.v b/hw/application_fpga/rtl/clk_reset_gen.v
index 4466f75..d01bf84 100644
--- a/hw/application_fpga/rtl/clk_reset_gen.v
+++ b/hw/application_fpga/rtl/clk_reset_gen.v
@@ -68,7 +68,7 @@ module clk_reset_gen #(parameter RESET_CYCLES = 200)
   SB_PLL40_CORE #(
 		  .FEEDBACK_PATH("SIMPLE"),
 		  .DIVR(4'b0000),	// DIVR =  0
-		  .DIVF(7'b0101111),	// DIVF = 47
+		  .DIVF(7'b0110111),	// DIVF = 55
 		  .DIVQ(3'b101),	// DIVQ =  5
 		  .FILTER_RANGE(3'b001)	// FILTER_RANGE = 1
 		  ) pll_inst (