From 875ba08299593c0e260e61c1332840908be1ed4f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joachim=20Str=C3=B6mbergson?= Date: Mon, 15 Apr 2024 15:07:45 +0200 Subject: [PATCH] Increase clock frequency to 21 MHz MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Joachim Strömbergson --- hw/application_fpga/rtl/clk_reset_gen.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/application_fpga/rtl/clk_reset_gen.v b/hw/application_fpga/rtl/clk_reset_gen.v index 4466f75..d01bf84 100644 --- a/hw/application_fpga/rtl/clk_reset_gen.v +++ b/hw/application_fpga/rtl/clk_reset_gen.v @@ -68,7 +68,7 @@ module clk_reset_gen #(parameter RESET_CYCLES = 200) SB_PLL40_CORE #( .FEEDBACK_PATH("SIMPLE"), .DIVR(4'b0000), // DIVR = 0 - .DIVF(7'b0101111), // DIVF = 47 + .DIVF(7'b0110111), // DIVF = 55 .DIVQ(3'b101), // DIVQ = 5 .FILTER_RANGE(3'b001) // FILTER_RANGE = 1 ) pll_inst (