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Increase clock frequency to 21 MHz 

Signed-off-by: Joachim Strömbergson <joachim@assured.se>
This commit is contained in:
Joachim Strömbergson 2024-04-15 15:07:45 +02:00
parent 3cf218469c
commit 875ba08299
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GPG Key ID: 865B8A548EA61679
1 changed files with 1 additions and 1 deletions
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2
hw/application_fpga/rtl/clk_reset_gen.v
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@ -68,7 +68,7 @@ module clk_reset_gen #(parameter RESET_CYCLES = 200)
SB_PLL40_CORE #(
.FEEDBACK_PATH("SIMPLE"),
.DIVR(4'b0000), // DIVR = 0
.DIVF(7'b0101111), // DIVF = 47
.DIVF(7'b0110111), // DIVF = 55
.DIVQ(3'b101), // DIVQ = 5
.FILTER_RANGE(3'b001) // FILTER_RANGE = 1
) pll_inst (