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FPGA: Increase clock frequency to 21 MHz

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Signed-off-by: Joachim Strömbergson <joachim@assured.se>
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Joachim Strömbergson 2024-06-17 15:28:57 +02:00 • committed by Daniel Jobson
parent 00599549e3
commit 75b028505f
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3 changed files with 9 additions and 9 deletions
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10
hw/application_fpga/rtl/clk_reset_gen.v
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@ -70,14 +70,14 @@ module clk_reset_gen #(parameter RESET_CYCLES = 200)
//
// F_pllout == (F_referenceclk * (DIVF + 1)) / (2^DIVQ * (DIVR + 1))
//
// Given the 12 MHz HFOSC clock set above, we get a final 18 MHz:
// Given the 12 MHz HFOSC clock set above, we get a final 21 MHz:
//
// (12000000 * (47 + 1)) / (2^5 * (0 + 1)) = 18000000
// (12000000 * (55 + 1)) / (2^5 * (0 + 1)) = 21000000
SB_PLL40_CORE #(
.FEEDBACK_PATH("SIMPLE"),
.DIVR(4'b0000), // DIVR = 0
.DIVF(7'b0101111), // DIVF = 47
.DIVQ(3'b101), // DIVQ = 5
.DIVR(4'd0), // DIVR = 0
.DIVF(7'd55), // DIVF = 55
.DIVQ(3'd5), // DIVQ = 5
.FILTER_RANGE(3'b001) // FILTER_RANGE = 1
) pll_inst (
.RESETB(1'b1),