mirror of
https://github.com/tillitis/tillitis-key1.git
synced 2024-12-11 17:04:28 -05:00
138 lines
3.9 KiB
Verilog
138 lines
3.9 KiB
Verilog
//======================================================================
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//
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// clk_reset_gen.v
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// -----------
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// Clock and reset generator used in the Tillitis Key 1 design.
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// This module instantiate the internal SB_HFOSC clock source in the
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// Lattice ice40 UP device. It then connects it to the PLL, and
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// finally connects the output from the PLL to the global clock net.
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//
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//
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// Author: Joachim Strombergson
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// Copyright (C) 2022 - Tillitis AB
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// SPDX-License-Identifier: GPL-2.0-only
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//
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//======================================================================
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`default_nettype none
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module clk_reset_gen #(parameter RESET_CYCLES = 200)
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(
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input wire sys_reset,
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output wire clk,
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output wire rst_n
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);
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//----------------------------------------------------------------
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// Registers with associated wires.
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//----------------------------------------------------------------
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reg [7 : 0] rst_ctr_reg = 8'h0;
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reg [7 : 0] rst_ctr_new;
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reg rst_ctr_we;
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reg rst_n_reg = 1'h0;
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reg rst_n_new;
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reg sys_reset_reg;
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//----------------------------------------------------------------
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// Wires.
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//----------------------------------------------------------------
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wire hfosc_clk;
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wire pll_clk;
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//----------------------------------------------------------------
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// Concurrent assignment.
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//----------------------------------------------------------------
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assign rst_n = rst_n_reg;
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//----------------------------------------------------------------
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// Core instantiations.
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//----------------------------------------------------------------
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/* verilator lint_off PINMISSING */
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// Use the FPGA internal High Frequency OSCillator as clock source.
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// 00: 48MHz, 01: 24MHz, 10: 12MHz, 11: 6MHz
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SB_HFOSC #(.CLKHF_DIV("0b10")
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) hfosc_inst (.CLKHFPU(1'b1),.CLKHFEN(1'b1),.CLKHF(hfosc_clk));
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// Use a PLL to generate a new clock frequency based on the HFOSC clock.
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//
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// Given FEEDBACK_PATH=="SIMPLE", clock calculation according to 3.5.2 in
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// FPGA-TN-02052-1-4-iCE40-sysCLOCK-PLL-Design-User-Guide.pdf
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// https://www.latticesemi.com/view_document?document_id=47778 follows:
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//
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// F_pllout == (F_referenceclk * (DIVF + 1)) / (2^DIVQ * (DIVR + 1))
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//
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// Given the 12 MHz HFOSC clock set above, we get a final 21 MHz:
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//
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// (12000000 * (55 + 1)) / (2^5 * (0 + 1)) = 21000000
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SB_PLL40_CORE #(
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.FEEDBACK_PATH("SIMPLE"),
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.DIVR(4'd0), // DIVR = 0
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.DIVF(7'd55), // DIVF = 55
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.DIVQ(3'd5), // DIVQ = 5
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.FILTER_RANGE(3'b001) // FILTER_RANGE = 1
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) pll_inst (
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.RESETB(1'b1),
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.BYPASS(1'b0),
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.REFERENCECLK(hfosc_clk),
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.PLLOUTCORE(pll_clk)
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);
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// Use a Global Buffer to distribute the clock.
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SB_GB gb_inst (
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.USER_SIGNAL_TO_GLOBAL_BUFFER (pll_clk),
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.GLOBAL_BUFFER_OUTPUT (clk)
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);
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/* verilator lint_on PINMISSING */
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//----------------------------------------------------------------
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// reg_update.
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//----------------------------------------------------------------
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always @(posedge clk)
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begin : reg_update
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rst_n_reg <= rst_n_new;
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sys_reset_reg <= sys_reset;
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if (rst_ctr_we)
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rst_ctr_reg <= rst_ctr_new;
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end
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//----------------------------------------------------------------
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// rst_logic.
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//----------------------------------------------------------------
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always @*
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begin : rst_logic
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rst_n_new = 1'h1;
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rst_ctr_new = 8'h0;
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rst_ctr_we = 1'h0;
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if (sys_reset_reg) begin
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rst_ctr_new = 8'h0;
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rst_ctr_we = 1'h1;
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end
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else if (rst_ctr_reg < RESET_CYCLES) begin
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rst_n_new = 1'h0;
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rst_ctr_new = rst_ctr_reg + 1'h1;
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rst_ctr_we = 1'h1;
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end
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end
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endmodule // reset_gen
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//======================================================================
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// EOF reset_gen.v
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//======================================================================
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