From 75b028505f0d6dc685d37b84d73ddb9db5ee7ea2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joachim=20Str=C3=B6mbergson?= Date: Mon, 17 Jun 2024 15:28:57 +0200 Subject: [PATCH] FPGA: Increase clock frequency to 21 MHz MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Joachim Strömbergson --- hw/application_fpga/application_fpga.bin.sha256 | 2 +- hw/application_fpga/core/uart/rtl/uart.v | 6 +++--- hw/application_fpga/rtl/clk_reset_gen.v | 10 +++++----- 3 files changed, 9 insertions(+), 9 deletions(-) diff --git a/hw/application_fpga/application_fpga.bin.sha256 b/hw/application_fpga/application_fpga.bin.sha256 index 1e46e0a..f4360e1 100644 --- a/hw/application_fpga/application_fpga.bin.sha256 +++ b/hw/application_fpga/application_fpga.bin.sha256 @@ -1 +1 @@ -24e642b0dc78a7dbf4cd87c223dd26eefb1ad444c96858e1c2b373f35701ccc0 application_fpga.bin +42746c6d9d879ad975874fb51b3d4e031578dac9a0e7ddd4b10a1d3efa34c6c7 application_fpga.bin diff --git a/hw/application_fpga/core/uart/rtl/uart.v b/hw/application_fpga/core/uart/rtl/uart.v index b2d0364..d5515d2 100644 --- a/hw/application_fpga/core/uart/rtl/uart.v +++ b/hw/application_fpga/core/uart/rtl/uart.v @@ -83,10 +83,10 @@ module uart( // The default bit rate is based on target clock frequency // divided by the bit rate times in order to hit the // center of the bits. I.e. - // Clock: 18 MHz, 62500 bps - // Divisor = 18E6 / 62500 = 288 + // Clock: 21 MHz, 62500 bps + // Divisor = 21E6 / 62500 = 336 // This also satisfies 1E6 % bps == 0 for the CH552 MCU used for USB-serial - localparam DEFAULT_BIT_RATE = 16'd288; + localparam DEFAULT_BIT_RATE = 16'd336; localparam DEFAULT_DATA_BITS = 4'h8; localparam DEFAULT_STOP_BITS = 2'h1; diff --git a/hw/application_fpga/rtl/clk_reset_gen.v b/hw/application_fpga/rtl/clk_reset_gen.v index 820b0d6..7f7f4d3 100644 --- a/hw/application_fpga/rtl/clk_reset_gen.v +++ b/hw/application_fpga/rtl/clk_reset_gen.v @@ -70,14 +70,14 @@ module clk_reset_gen #(parameter RESET_CYCLES = 200) // // F_pllout == (F_referenceclk * (DIVF + 1)) / (2^DIVQ * (DIVR + 1)) // - // Given the 12 MHz HFOSC clock set above, we get a final 18 MHz: + // Given the 12 MHz HFOSC clock set above, we get a final 21 MHz: // - // (12000000 * (47 + 1)) / (2^5 * (0 + 1)) = 18000000 + // (12000000 * (55 + 1)) / (2^5 * (0 + 1)) = 21000000 SB_PLL40_CORE #( .FEEDBACK_PATH("SIMPLE"), - .DIVR(4'b0000), // DIVR = 0 - .DIVF(7'b0101111), // DIVF = 47 - .DIVQ(3'b101), // DIVQ = 5 + .DIVR(4'd0), // DIVR = 0 + .DIVF(7'd55), // DIVF = 55 + .DIVQ(3'd5), // DIVQ = 5 .FILTER_RANGE(3'b001) // FILTER_RANGE = 1 ) pll_inst ( .RESETB(1'b1),