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Verilog 2001 rule; use wires for assignments, not registers. (#139)

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blaufish 2023-08-16 10:44:18 +02:00 committed by GitHub
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commit 426b56ebf5
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hw/application_fpga/rtl/fw_ram.v
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@ -35,7 +35,7 @@ module fw_ram(
reg [31 : 0] mem_read_data0; reg [31 : 0] mem_read_data0;
reg [31 : 0] mem_read_data1; reg [31 : 0] mem_read_data1;
reg ready_reg; reg ready_reg;
reg fw_app_cs; wire fw_app_cs;
reg bank0; reg bank0;
reg bank1; reg bank1;