From 426b56ebf52c9cb3cbdfae51e4b5b15c2094aebb Mon Sep 17 00:00:00 2001
From: blaufish <blaufish@users.noreply.github.com>
Date: Wed, 16 Aug 2023 10:44:18 +0200
Subject: [PATCH] Verilog 2001 rule; use wires for assignments, not registers.
 (#139)

---
 hw/application_fpga/rtl/fw_ram.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/application_fpga/rtl/fw_ram.v b/hw/application_fpga/rtl/fw_ram.v
index 32dee42..6311b6b 100644
--- a/hw/application_fpga/rtl/fw_ram.v
+++ b/hw/application_fpga/rtl/fw_ram.v
@@ -35,7 +35,7 @@ module fw_ram(
   reg [31 : 0] mem_read_data0;
   reg [31 : 0] mem_read_data1;
   reg          ready_reg;
-  reg          fw_app_cs;
+  wire         fw_app_cs;
   reg          bank0;
   reg          bank1;