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https://github.com/tillitis/tillitis-key1.git
synced 2024-10-01 01:45:38 -04:00
(fpga) Possibly working syscall hw functionality.
We don't want to set which address the CPU should jump to when a syscall is made, we want to push the jump instruction to execute. If that works. Signed-off-by: Joachim Strömbergson <joachim@assured.se>
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@ -26,7 +26,7 @@ module tk1(
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output wire force_trap,
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output system_reset,
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output wire [31 : 0] syscall_addr,
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output wire [31 : 0] syscall_instr,
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output wire syscall,
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output wire [14 : 0] ram_addr_rand,
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@ -84,7 +84,7 @@ module tk1(
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localparam ADDR_BLAKE2S = 8'h10;
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localparam ADDR_SYSCALL_ADDR = 8'h12;
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localparam ADDR_SYSCALL_INSTR = 8'h12;
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localparam ADDR_SYSCALL_START = 8'h13;
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localparam ADDR_CDI_FIRST = 8'h20;
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@ -144,8 +144,11 @@ module tk1(
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reg [31 : 0] blake2s_addr_reg;
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reg blake2s_addr_we;
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reg [31 : 0] syscall_addr_reg;
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reg syscall_addr_we;
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reg [31 : 0] syscall_instr_reg;
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reg syscall_instr_we;
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reg syscall_reg;
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reg syscall_new;
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reg [23 : 0] cpu_trap_ctr_reg;
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reg [23 : 0] cpu_trap_ctr_new;
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@ -215,8 +218,8 @@ module tk1(
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assign system_reset = system_reset_reg;
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assign syscall_addr = syscall_addr_reg;
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assign syscall = start_syscall;
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assign syscall_instr = syscall_instr_reg;
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assign syscall = syscall_reg;
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//----------------------------------------------------------------
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@ -282,7 +285,8 @@ module tk1(
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app_start_reg <= 32'h0;
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app_size_reg <= 32'h0;
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blake2s_addr_reg <= 32'h0;
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syscall_addr_reg <= 32'h0;
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syscall_instr_reg <= 32'h0;
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syscall_reg <= 1'h0;
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cdi_mem[0] <= 32'h0;
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cdi_mem[1] <= 32'h0;
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cdi_mem[2] <= 32'h0;
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@ -306,6 +310,7 @@ module tk1(
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cpu_trap_ctr_reg <= cpu_trap_ctr_new;
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system_reset_reg <= system_reset_new;
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syscall_reg <= syscall_new;
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gpio1_reg[0] <= gpio1;
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gpio1_reg[1] <= gpio1_reg[0];
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@ -341,8 +346,8 @@ module tk1(
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blake2s_addr_reg <= write_data;
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end
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if (syscall_addr_we) begin
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syscall_addr_reg <= write_data;
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if (syscall_instr_we) begin
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syscall_instr_reg <= write_data;
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end
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if (cdi_mem_we) begin
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@ -455,8 +460,8 @@ module tk1(
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app_start_we = 1'h0;
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app_size_we = 1'h0;
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blake2s_addr_we = 1'h0;
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syscall_addr_we = 1'h0;
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start_syscall = 1'h0;
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syscall_instr_we = 1'h0;
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syscall_new = 1'h0;
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cdi_mem_we = 1'h0;
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cdi_mem_we = 1'h0;
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ram_addr_rand_we = 1'h0;
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@ -516,14 +521,14 @@ module tk1(
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end
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end
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if (address == ADDR_SYSCALL_ADDR) begin
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if (address == ADDR_SYSCALL_INSTR) begin
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if (!switch_app_reg) begin
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syscall_addr_we = 1'h1;
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syscall_instr_we = 1'h1;
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end
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end
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if (address == ADDR_SYSCALL_START) begin
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start_syscall = 1'h1;
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syscall_new = 1'h1;
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end
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if ((address >= ADDR_CDI_FIRST) && (address <= ADDR_CDI_LAST)) begin
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@ -149,7 +149,7 @@ module application_fpga(
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wire [14 : 0] ram_addr_rand;
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wire [31 : 0] ram_data_rand;
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wire tk1_system_reset;
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wire [31 : 0] tk1_syscall_addr;
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wire [31 : 0] tk1_syscall_instr;
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wire tk1_syscall;
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/* verilator lint_on UNOPTFLAT */
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@ -330,7 +330,7 @@ module application_fpga(
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.system_reset(tk1_system_reset),
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.syscall_addr(tk1_syscall_addr),
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.syscall_instr(tk1_syscall_instr),
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.syscall(tk1_syscall),
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.ram_addr_rand(ram_addr_rand),
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@ -439,6 +439,12 @@ module application_fpga(
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muxed_rdata_new = ILLEGAL_INSTRUCTION;
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muxed_ready_new = 1'h1;
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end
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else if (tk1_syscall) begin
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muxed_rdata_new = tk1_syscall_instr;
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muxed_ready_new = 1'h1;
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end
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else begin
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case (area_prefix)
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ROM_PREFIX: begin
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@ -448,16 +454,10 @@ module application_fpga(
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end
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RAM_PREFIX: begin
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if (tk1_syscall) begin
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muxed_rdata_new = tk1_syscall_addr;
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muxed_ready_new = 1'h1;
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end
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else begin
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ram_cs = 1'h1;
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ram_we = cpu_wstrb;
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muxed_rdata_new = ram_read_data ^ ram_data_rand ^ {2{cpu_addr[15 : 0]}};
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muxed_ready_new = ram_ready;
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end
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ram_cs = 1'h1;
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ram_we = cpu_wstrb;
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muxed_rdata_new = ram_read_data ^ ram_data_rand ^ {2{cpu_addr[15 : 0]}};
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muxed_ready_new = ram_ready;
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end
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RESERVED_PREFIX: begin
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