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tillitis-key/hw/application_fpga/core
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Daniel Jobson d9d41811bd
tb: fix tk1 testbench after name change 
This issue was introduced in commit 53c5e707, after name change of RAM
randomization API.
2024-10-11 15:50:07 +02:00
..
clk_reset_gen
Doc: Add README for the clock and reset core.
2024-08-29 16:06:59 +02:00
fw_ram
Doc: Add README for the fw_ram.
2024-08-29 16:06:59 +02:00
picorv32
FPGA: Ignore warnings about blocking assignment in clocked processes
2024-06-17 15:37:13 +02:00
ram
FPGA: Move RAM address and data scrambling into the RAM module.
2024-08-30 10:53:13 +02:00
rom
Doc: Add README for the ROM core.
2024-08-29 16:06:59 +02:00
timer
Update Verilog version to 2005 for linting
2024-04-24 08:44:08 +02:00
tk1
tb: fix tk1 testbench after name change
2024-10-11 15:50:07 +02:00
touch_sense
Update Verilog version to 2005 for linting
2024-04-24 08:44:08 +02:00
trng
Update Verilog version to 2005 for linting
2024-04-24 08:44:08 +02:00
uart
FPGA: Increase clock frequency to 21 MHz
2024-08-20 13:45:00 +02:00
uds
Remove YosysHQ copyright and fix name typo
2024-09-30 15:01:31 +02:00