Joachim Strömbergson d6e0d90dfd

First attempt at supporting host based reset ...

The feature enables the interface_rts signal from the CH552 MCU in
constraints as well as inte FPGA interface. The signal is routed into
the clk_reset_gen block where it is sampled. If the sampled signal is
set, a system reset is triggered

Signed-off-by: Joachim Strömbergson <joachim@assured.se>

2024-04-22 16:14:10 +02:00

..

application_fpga_mta1_usb_dev.pcf

Rename to TK1

2022-10-26 09:20:02 +02:00

application_fpga_tk1.pcf

First attempt at supporting host based reset

2024-04-22 16:14:10 +02:00

udi.hex

Make initial public release

2022-09-19 08:51:11 +02:00

uds.hex

Use different byte values in test UDS words

2023-03-28 09:26:23 +02:00