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d6e0d90dfd
The feature enables the interface_rts signal from the CH552 MCU in constraints as well as inte FPGA interface. The signal is routed into the clk_reset_gen block where it is sampled. If the sampled signal is set, a system reset is triggered Signed-off-by: Joachim Strömbergson <joachim@assured.se> |
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| production_test | ||