blaufish cced6aec31 Explicity make uart_core.rx_data a wire (#140)		2023-08-16 10:43:04 +02:00
..
core	Explicity make uart_core.rx_data a wire (#140)	2023-08-16 10:43:04 +02:00
data	Change name of pin constraint file to match tk1 pcb	2023-07-04 09:04:29 +02:00
fw	Make memeq function side channel silent	2023-07-04 09:04:23 +02:00
rtl	bank1 access should also be disabled by default.	2023-03-13 12:43:07 +01:00
tb	Rename to TK1	2022-10-26 09:20:02 +02:00
tools	Correct to new path	2023-01-13 15:42:46 +01:00
application_fpga.bin.sha256	Use tkey-builder:2; add hashes & checks for bitstream & fw bins	2023-07-04 09:04:23 +02:00
config.vlt	Config verilator lint to ignore known 3rd-party warnings; let warnings be fatal	2023-03-01 13:37:31 +01:00
firmware.bin.sha512	Use tkey-builder:2; add hashes & checks for bitstream & fw bins	2023-07-04 09:04:23 +02:00
Makefile	Change name of pin constraint file to match tk1 pcb	2023-07-04 09:04:29 +02:00