tillitis-key/core at cbb2ba7512c192553254c7a78e89ebd8c8d7b70b - tillitis-key - Gitea: Git with a cup of tea

Git-Mirrors/tillitis-key

mirror of https://github.com/tillitis/tillitis-key1.git synced 2025-01-29 08:43:33 -05:00

History

Daniel Jobson cbb2ba7512

Doc: fix typo in tk1 core readme

2024-10-11 15:50:07 +02:00

..

Doc: Add README for the clock and reset core.

2024-08-29 16:06:59 +02:00

Doc: Add README for the fw_ram.

2024-08-29 16:06:59 +02:00

FPGA: Ignore warnings about blocking assignment in clocked processes

2024-06-17 15:37:13 +02:00

FPGA: Move RAM address and data scrambling into the RAM module.

2024-08-30 10:53:13 +02:00

Doc: Add README for the ROM core.

2024-08-29 16:06:59 +02:00

Update Verilog version to 2005 for linting

2024-04-24 08:44:08 +02:00

Doc: fix typo in tk1 core readme

2024-10-11 15:50:07 +02:00

Update Verilog version to 2005 for linting

2024-04-24 08:44:08 +02:00

Update Verilog version to 2005 for linting

2024-04-24 08:44:08 +02:00

FPGA: Increase clock frequency to 21 MHz

2024-08-20 13:45:00 +02:00

Remove YosysHQ copyright and fix name typo

2024-09-30 15:01:31 +02:00