Joachim Strömbergson c9f5173c18 Doc: Add README for the clock and reset core. ... Signed-off-by: Joachim Strömbergson <joachim@assured.se>		2024-08-29 16:06:59 +02:00
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clk_reset_gen	Doc: Add README for the clock and reset core.	2024-08-29 16:06:59 +02:00
fw_ram/rtl	FPGA: Move all sub modules into separate cores	2024-08-29 16:06:58 +02:00
picorv32	FPGA: Ignore warnings about blocking assignment in clocked processes	2024-06-17 15:37:13 +02:00
ram/rtl	FPGA: Move all sub modules into separate cores	2024-08-29 16:06:58 +02:00
rom/rtl	FPGA: Move all sub modules into separate cores	2024-08-29 16:06:58 +02:00
timer	Update Verilog version to 2005 for linting	2024-04-24 08:44:08 +02:00
tk1	FPGA: Add system reset API	2024-08-20 13:25:22 +02:00
touch_sense	Update Verilog version to 2005 for linting	2024-04-24 08:44:08 +02:00
trng	Update Verilog version to 2005 for linting	2024-04-24 08:44:08 +02:00
uart	FPGA: Increase clock frequency to 21 MHz	2024-08-20 13:45:00 +02:00
uds	Update Verilog version to 2005 for linting	2024-04-24 08:44:08 +02:00