Jonas Thörnblad 6566719317

Add complete checks for invalid memory accesses ...

Also fix two typos for memory ranges that fortunately
have no impact on functionality.

2025-02-03 13:39:33 +01:00

..

clk_reset_gen

FPGA: Format verilog code

2024-10-22 12:04:19 +02:00

fw_ram

Doc: fix typo of system mode in readme

2024-11-13 14:13:02 +01:00

picorv32

FPGA: Ignore warnings about blocking assignment in clocked processes

2024-06-17 15:37:13 +02:00

ram

Doc: move implementation details of RAM scrambling to RAM core

2024-11-20 15:48:49 +01:00

rom

Fix typo

2024-11-14 16:35:50 +01:00

timer

tb: make timer core testbench selftesting

2024-11-27 08:10:15 +01:00

tk1

Add complete checks for invalid memory accesses

2025-02-03 13:39:33 +01:00

touch_sense

tb: Make touch_sense selftesting

2024-12-09 13:55:42 +01:00

trng

tb: Make trng selftesting

2024-12-09 13:55:43 +01:00

uart

tb: Make uart selftesting

2024-12-09 13:55:43 +01:00

uds

Harmonize the naming of firmware and app mode.

2024-11-12 15:13:59 +01:00