Joachim Strömbergson c0a79e77c6 fpga: Add stateful access control ... Add access stateful control register that toggles if access to a resources is granted based on if code is excuted from ROM or RAM. The register is used to enable or block access to SPI but potentially other HW resources. Signed-off-by: Joachim Strömbergson <joachim@assured.se>		2024-08-22 11:29:44 +02:00
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picorv32	FPGA: Ignore warnings about blocking assignment in clocked processes	2024-06-17 15:37:13 +02:00
timer	Update Verilog version to 2005 for linting	2024-04-24 08:44:08 +02:00
tk1	fpga: Add stateful access control	2024-08-22 11:29:44 +02:00
touch_sense	Update Verilog version to 2005 for linting	2024-04-24 08:44:08 +02:00
trng	Update Verilog version to 2005 for linting	2024-04-24 08:44:08 +02:00
uart	FPGA: Increase clock frequency to 21 MHz	2024-08-20 13:45:00 +02:00
uds	Update Verilog version to 2005 for linting	2024-04-24 08:44:08 +02:00