Joachim Strömbergson b5ba21148d

FPGA: Cleanup tk1 spi testbench ...

- Remove DUT variables from state display that was removed as part of
  performance fix
- Corrected some incorrect display statements for expected unique ID and
  byte counters

Co-authored-by: Daniel Jobson <jobson@tillitis.se>
Signed-off-by: Joachim Strömbergson <joachim@assured.se>

2024-07-11 09:39:31 +02:00

..

picorv32

FPGA: Ignore warnings about blocking assignment in clocked processes

2024-06-17 15:37:13 +02:00

timer

Update Verilog version to 2005 for linting

2024-04-24 08:44:08 +02:00

tk1

FPGA: Cleanup tk1 spi testbench

2024-07-11 09:39:31 +02:00

touch_sense

Update Verilog version to 2005 for linting

2024-04-24 08:44:08 +02:00

trng

Update Verilog version to 2005 for linting

2024-04-24 08:44:08 +02:00

uart

Update Verilog version to 2005 for linting

2024-04-24 08:44:08 +02:00

uds

Update Verilog version to 2005 for linting

2024-04-24 08:44:08 +02:00